Generation of Checkpoints for Hardware Architecture Simulators

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Typ Bachelorarbeit oder Masterarbeit
Aushang Generation of checkpoints for hardware architecture simulators.pdf
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Sebastian Weber (E-Mail:, Telefon: +49-721-9654-622)


Hardware architecture simulators allow the precise analysis of the properties of different hardware architectures without the need to actually build and test them. Therefore they are also valuable tools for the analysis of existing systems, e.g., to gather information for a hardware migration. The drawback of these tools is their high execution time. To mitigate this drawback, some hardware architecture simulators allow to generate checkpoints from which a simulation can be started. This checkpoint generation is based on simulating the system until a certain point and then extracting the state of the simulated hardware and simulation. Thus it requires the execution of the simulation up to this point once.


The goal of this thesis is to develop a concept for the generation of simulator checkpoints without the need to simulate the system in the simulator. This includes:

  • Overview of required information to generate a checkpoint across different hardware architecture simulators
  • Overview of sources of the required information to generate a checkpoint
  • Concept and prototypical implementation of an information extraction from one or more of the identified sources
  • Concept and prototypical implementation of a checkpoint generator


  • Introduction to the field of modelling and simulation
  • Close connection to ongoing research projects
  • Excellent working environment and intensive support (German or English)